1. Field of the Invention
The present invention relates to a semiconductor memory having a plurality of memory cells.
2. Description of the Related Art
Two main types of memory are used to store digital information in electronic devices. One type uses mechanisms such as magnetic or optical disk drives that require physical motion. The other type uses semiconductor memory elements that do not require physical motion. Semiconductor memory can be further classified as volatile, meaning that the stored information is lost when power is switched off, or nonvolatile, meaning that the stored information is retained even while power is off.
In a nonvolatile memory such as an erasable programmable read only memory (EPROM) each memory cell typically has a single charge-storage region. The original or non-programmed state in which no charge is stored in the charge storage region is defined as the ‘1’ state; the written state or programmed state, in which negative charge is stored in the charge storage region, increasing the threshold voltage of the memory cell, is defined as the ‘0’ state. Such a memory cell has, for example, an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure including a gate oxide film. The charge storage region is then a floating gate (FG) made of polysilicon, buried in the gate oxide film and electrically isolated from other regions. Such a memory cell can be programmed, read, and erased in, for example, the following way.
To program the memory cell, that is, to write ‘0’ data into the floating gate, positive voltages are applied to the drain and control gate of the memory cell while the source is grounded. With this biasing, electrons traveling in the channel from the source to the drain acquire high kinetic energy in the vicinity of the drain, becoming so-called hot electrons. Some of these hot electrons pass through the gate oxide film and are injected into the floating gate and held there. When the floating gate has stored a sufficient charge in this way, the writing of ‘0’ data is completed.
Since the electrons injected into the floating gate are negatively charged, after the writing operation, the threshold voltage of the memory cell observed at the control gate is higher than before. To read the data in the memory cell, a voltage intermediate between the threshold voltages before and after programming is applied to the control gate, a positive voltage is applied to the drain, and the source is grounded. If the memory cell has been programmed to the ‘0’ state, no current flows through it, because the voltage applied to the control gate is lower than the threshold voltage in the programmed state. If the memory cell has not been programmed and is still in the ‘1’ state, it conducts current because the voltage applied to its control gate is higher than its threshold voltage. The value of the data stored in the memory cell is read by detecting the current or the absence thereof.
To erase the data stored in the memory device, the memory cells are irradiated with, for example, ultraviolet light. This brings the electrons stored in the floating gates into a high energy state, enabling the electrons to escape through the gate oxide films into the substrate and the control gates. The floating gates thereby lose their negative charge and the memory cells are returned to their original non-programmed state.
In Japanese Patent Application Publication No. 2008-47224, Kuramori describes an EPROM in which memory cells of this type are arranged in a matrix to form a memory array and the memory cells in the memory array are connected to amplifiers by bit lines.
In a semiconductor memory, however, since adjacent bit lines are separated by a dielectric material, there is a parasitic capacitance between them, causing the following problem. When one bit line is selected, the voltage change on the selected bit line is coupled through the parasitic capacitance to the adjacent bit lines and the voltage on the adjacent bit lines also changes, causing current to flow on the adjacent bit lines as well as the selected bit line. When current is detected to read a memory cell in a nonvolatile semiconductor memory such as the above EPROM, accordingly, part of the detected current may be due to current flow through adjacent memory cells; it is difficult to detect current depending only on the selected or unselected state and threshold voltage of the intended memory cell. Accordingly, there is the risk of reading data incorrectly due to the effect of the parasitic capacitance between the bit lines. This problem can also occur in volatile semiconductor memory,
This problem can be solved by additionally providing, between each pair of adjacent bit lines, a line that is tied to a fixed potential such as the ground potential, but this solution is incompatible with small circuit size. The small form factors of recent non-volatile and volatile semiconductor memories make the insertion of such additional lines between the bit lines extremely difficult.